Mixed Level and Mixed Signal Simulation using PSpice A/D and VHDL

ID#413 – Author: Sreeram Rajagopalan 2 1. ABSTRACT PSpice A/D is a simulation package that is used to analyze and predict the performance of analog and mixed signal circuits. It is very popular especially among Printed Circuit Board (PCB) engineers to verify board level designs. However, PSpice A/D currently lacks the ability to simulate analog components connected to digital circuits that are modeled using Hardware Descriptive Languages (HDLs), such as VHDL and Verilog HDL. Simulation of HDL models in PSpice A/D is necessary to verify mixed signal PCBs where programmable logic devices like Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs) are connected to discrete analog components. More than 60% of the PCBs that are designed today contain at least one FPGA or CPLD. This paper investigates the possibility of simulating VHDL models in PSpice A/D. A new design methodology and the necessary tools to achieve this goal are presented. The new design methodology will help engineers verify a complete mixed signal design at the board level. This reduces design failures and hence increases reliability. It also reduces the overall time to market. A mixed signal design from NASA Goddard Space Flight Center for a brushless three phase motor that runs a space application is implemented by following the proposed design methodology. 2. INTRODUCTION Over the past few decades, Printed Circuit Boards (PCBs) have brought significant change and advancement to the electronics industry. The overall cost, shape and size of many modern day electronic equipments are dependent on the size and complexity of the PCB that is utilized. A complex board can contain printed circuitry on both its sides or in many layers, which allows great circuit density and compactness. With the increase in the complexity and reduced time to market, Computer Aided Design (CAD) tools are required to design PCBs, and the need for the CAD tool to support and automate complex design tasks have always remained persistent [7]. The Complexity of the design, necessity to increase design efficiency and to reduce time to design, drives the circuit design methodology and the choice of Electronic Design Automation (EDA) tools. Design methodologies are typically classified into Top down design methodology enables designers to refine an abstract idea progressively as the design process continues. The design process could begin with a very high level behavioral definition of the system and then it can get down to finer details with Register Transfer Level (RTL) and gate level descriptions, as the design progresses. This methodology is more popular with digital circuit designs with the advent of HDLs, Programmable Logic Devices (PLDs) and logic synthesis tools [9]. Traditional or bottom up design methodology allows designers to pick components individually (from a standard set of libraries) and build the design by connecting them appropriately. This methodology is popular in the PCB design flow [11]. Large and complex systems are usually broken into smaller units. These units can be designed using different methodologies. Due to difference in levels of design abstraction, different EDA tools are required to work with different design methodologies. This curtails the ability to verify the functionality of the whole system, which is a potential cause for design failures. Moreover a majority of today’s designs are mixed signal circuits, circuits containing different signal domains (eg. analog and digital). A typical example of such a design would be a PCB which has PLDs along with other discrete analog components. In awake of such scenarios, rises a need to have EDA tools that are capable of simulating mixed signal designs as well as designs designed using different methodologies. Such simulations are called mixed level and mixed signal simulation. PSpice A/D, which is very popular among PCB designer, supports mixed signal simulation using traditional design methodology. It however lacks the ability to simulate digital designs modeled using HDLs such as VHDL, Verilog etc. [10]. By enabling simulation of VHDL models in PSpice A/D it is possible to realize a mixed level simulator from a mixed signal simulator. This integrates traditional designing methodology with top down design methodology and hence helps in verifying the functionality of the whole system and identifying problems much earlier in the design cycles. AbstractID#413 – Author: Sreeram Rajagopalan 3ID#413 – Author: Sreeram Rajagopalan 3 This paper proposes a new design methodology that will allow simulation of synthesizable VHDL models in PSpice A/D along with discrete analog circuits and provides a low-cost solution for simulating mixed signal designs containing VHDL models for FPGAs and/or CPLDs. However the simulation time of such designs will be directly proportional to the number of gates produced after synthesizing the RTL VHDL. 3. PROPOSED DESIGN METHODOLOGY A design methodology to achieve total system verification at a board level is presented in figure 1. The complex mixed signal design is divided into two sections, namely analog and digital. While the analog circuits are designed by following the traditional design methodology using PSpice A/D schematic editor, the digital portion in VHDL follows the top down design methodology. Finally, the interfacing software (See Section 3B) abridges the two design methodologies by enabling functional verification of the mixed signal design in PSpice A/D. Verification at PCB level requires the simulation medium to support multiple signal domains (analog and digital) along with different design methodologies (traditional/top down). PSpice A/D is a verification software that already supports mixed signal domains. However, it has limitations in design abstraction levels and most of its digital constructs are available only at gate level. The ability to simulate VHDL models in PSpice will allow verification of designs that are defined using different methodologies. To achieve this goal, the proposed methodology employs a logic synthesis tool (Synplify), which translates any (RTL) VHDL design into it’s equivalent gate level (VHDL) description. Logic synthesis retains the essence and rapidness of top down design methodology and allows engineers to describe designs in a high level abstract and be less concerned about the actual implementation. A synthesized VHDL description (gate level netlist) represents the digital system in terms of logic gates and the synthesis tool, Synplify generates a gate level VHDL description that is specific to a technology (FPGA, CPLDs architectures from vendors like Xilinx, Altera, Actel etc.) that was chosen during the logic synthesis process. In order to simulate this gate level VHDL description in PSpice A/D, the resulting netlist needs to be in a format that is understood by the PSpice simulation engine. In other words, the gate level VHDL netlist requires to be translated into a PSpice subcircuit definition. Besides this requirement, simulation of technology-specific gate level VHDL description in PSpice also requires the need for appropriate digital device models within PSpice model libraries. The choice of the technology during logic synthesis determines the ease of translation and the ability to avail or create digital device models in PSpice. Typically, CPLD architectures are relatively simple when compared with FPGAs. CPLDs implement digital circuitry in terms of combinatorial and sequential logic functions. Considering these factors the digital logic described in VHDL is synthesized by targeting at Lattice MACH 111 family of CPLDs. The gate level VHDL description generated by Synplify (synthesis tool) can be translated into a PSpice subcircuit definition and it also contains digital devices that are either currently available or that can be modeled in PSpice A/D. The design flow in this proposed methodology is as follows The digital logic is described in VHDL and simulated to verify its functionality (top down design methodology) The RTL VHDL code is synthesized in Synplify using Lattice MACH 111 as the target technology. The gate level VHDL description (after synthesis) is functionally verified for logical equivalency [13]. The gate level netlist is now converted into a PSpice circuit file using the interfacing software which was developed as a part of this research. The Circuit file is converted into a schematic symbol which can be placed on OrCAD Capture (schematic editor) along with other analog components and the complete mixed signal design is verified by simulating in PSpice A/D The translation of the gate level VHDL netlist into its equivalent PSpice circuit file requires 1. A library of PSpice models for Lattice MACH 111 components. AbstractID#413 – Author: Sreeram Rajagopalan 4 2. Interfacing software that will utilize components from this library and create a PSpice subcircuit file from the gate level VHDL netlist.ID#413 – Author: Sreeram Rajagopalan 4 2. Interfacing software that will utilize components from this library and create a PSpice subcircuit file from the gate level VHDL netlist. Fig. 1. Proposed design methodology A. PSpice library of Lattice devices The gate level VHDL netlist generated by Synplify (synthesis tool) contains components specific to Lattice MACH 111 technology. The following set of combinational and sequential logic elements from the MACH 111 family are utilized by the interfacing software during the translation process. Combinational logic elements 1) IBUF Input Buffer 2) OBUF Output Buffer 3) INV Logic inverter 4) OR2 2 Input logic OR 5) XOR2 2 Input logic XOR 6) AND2 2 Input logic AND Sequential logic elements 1) MACHDFF Reset predominant D flip flop with low preset and reset AbstractID#413 – Author: Sreeram Rajagopalan 5 2) DFFRH Reset predominant D Flip flop with preset remaining HIGH all timesID#413 – Author: Sreeram Rajagopalan 5 2) DFFRH Reset predominant D Flip flop with preset remaining HIGH all times 3) DFFSH Reset predominant D Flip flop with reset remaining HIGH all times 4) DFF Reset predominant D Flip flop The functional behavior of these logic elements are modeled in PSpice and a library of device models is created for every component that is present in the gate level VHDL netlist. B. Interfacing software In the previous section, the creation of PSpice models for Lattice MACH digital devices was discussed. Next, the gate level VHDL netlist needs to be translated into a PSpice subcircuit file. A software program was developed to perform this task. This program will be the interface between the gate level VHDL description and PSpice A/D. Figure 2 presents a flow chart to translate gate level VHDL description into a PSpice circuit file. The gate level VHDL netlist follows a typical pattern of structured VHDL logic description (Component declaration and definition followed by the main entity and architecture). For every component defined in the gate level VHDL netlist, there exists an equivalent PSpice model. The interfacing program reads through the gate level VHDL netlist, identifies a Lattice MACH device and replaces it with its equivalent PSpice model in the subcircuit file which it writes simultaneously. The following procedure is followed by the interfacing software 1. Parse through the gate level VHDL netlist and skip until the Main Entity within the file is reached. 2. Within the Main Entity, extract the name of the inputs and outputs. If the inputs/outputs are declared as a BUS, elaborate the bus entries and assign individual net names for each one of the bus entries. PSpice digital device modeling language does not permit BUS declaration. 3. Using the input and output names obtained, define the subcircuit header in the PSpice circuit file by following the PSpice modeling language syntax. 4. Continue to parse the VHDL file and skip until the Main Architecture of the entity is reached. 5. Within the Main Architecture, skip the section where internal signal and component names are declared. 6. Scan the architectural definition and identify the Lattice MACH device that is being “port mapped” 7. Use “CASE” statements to map the identified component with its equivalent PSpice model. 8. Scan the “port mapping” definition to identify the input and output net names and assign them to appropriate PSpice model terminals. 9. Loop until the end of architecture section is reached. AbstractID#413 – Author: Sreeram Rajagopalan 6 Read VHDL fileID#413 – Author: Sreeram Rajagopalan 6 Read VHDL file Write PSpice Circuit File Input/Output declaration Read Main Entity Read Signal declaration